~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv b7fa590c93b0d8e3e647fb08ecf033e314ece360

~ruther/verilog-riscv-semestral-project

ref: b7fa590c93b0d8e3e647fb08ecf033e314ece360 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB

32ebeea6 — Rutherther 1 year, 7 months ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 1 year, 7 months ago

feat: add instruction decoder