~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 32ebeea65b555fea871d5d5f91c13b27efcc6e57

~ruther/verilog-riscv-semestral-project

ref: 32ebeea65b555fea871d5d5f91c13b27efcc6e57 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB

32ebeea6 — Rutherther 1 year, 7 months ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 1 year, 7 months ago

feat: add instruction decoder