~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
11422de0 — Rutherther 2 years ago
feat: store c results in memory addr 0
30a7f949 — Rutherther 2 years ago
feat: add basic testing programs