~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv adfdc041e204e13c59c32d866fb2ee288b272c57

~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 837 bytes

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 2 years ago

test: add basic testbenches