~ruther/verilog-riscv-semestral-project: src/ram.sv adfdc041e204e13c59c32d866fb2ee288b272c57

~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 498 bytes

ca9604e2 — Rutherther 2 years ago

fix: offset ram by bytes, not bits

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file