~ruther/verilog-riscv-semestral-project: src/cpu_types.sv adfdc041e204e13c59c32d866fb2ee288b272c57

~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 2 years ago

chore: add cpu types for various sources

Better orientation by name instead of
number