~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7

~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 1 year, 6 months ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 1 year, 7 months ago

test: add ram test