~ruther/verilog-riscv-semestral-project

ref: 94c41794fa83c9d5c25d362920dc2ee4b5d48288 verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 6.4 KiB 
tests: add more custom tests

tests: add register dump, printing

tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests

tests: add python test environment for custom tests
Do not follow this link