~ruther/verilog-riscv-semestral-project: src/control_unit.sv 938d89a274f0e1a4c50cc75857cffaa30e2d6f68

~ruther/verilog-riscv-semestral-project

ref: 938d89a274f0e1a4c50cc75857cffaa30e2d6f68 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB

52b05e5d — Rutherther 1 year, 7 months ago

feat: add control_unit wrapper over instruction_decoder