~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 332 bytes
feat: move jumping to execute stage
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
chore: add new files to compilation list
tests: add python test environment for custom tests
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