~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv 914e69e6c0df1f4e3f33718891c838e42fe535b1

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 5 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 5 months ago

test: add basic testbenches