~ruther/verilog-riscv-semestral-project: src 8adc02d7500da4fde40fb0b52d3078ab419e4e8f

~ruther/verilog-riscv-semestral-project

ref: 8adc02d7500da4fde40fb0b52d3078ab419e4e8f verilog-riscv-semestral-project/src d---------

8adc02d7 — Rutherther 1 year, 7 months ago

feat: add basic ram, alu, and register file