~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/tests/official/env/p/riscv_test.h -rwxr-xr-x 8.2 KiB 
tests: add register dump, printing

feat: add support for official tests
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