~ruther/verilog-riscv-semestral-project

ref: 89310129c1470fe2c2cdd10d9b6c88d5eab747cc verilog-riscv-semestral-project/tests/official/env d---------
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
51842d38 — Rutherther 2 years ago
feat: add support for official tests