~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv 89310129c1470fe2c2cdd10d9b6c88d5eab747cc

~ruther/verilog-riscv-semestral-project

ref: 89310129c1470fe2c2cdd10d9b6c88d5eab747cc verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 5 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 5 months ago

test: add basic testbenches