~ruther/verilog-riscv-semestral-project: src/ram.sv 82d9e44f3229f6554dade8f51988d313a1df02dc

~ruther/verilog-riscv-semestral-project

ref: 82d9e44f3229f6554dade8f51988d313a1df02dc verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file