~ruther/verilog-riscv-semestral-project: tests/test_types.py 7d544e62c57a7e944d1572d147f7b271333a75aa

~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/tests/test_types.py -rwxr-xr-x 928 bytes

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests