~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/tests/custom/custom_tests.py -rwxr-xr-x 1.8 KiB 
tests: add register dump, printing

feat: add support for official tests
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