~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/tests d--------- 
tests: add register dump, printing

tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests

tests: add python test environment for custom tests
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