~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 7d544e62c57a7e944d1572d147f7b271333a75aa

~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 1 year, 7 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number