~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv 7ad5176683d16ac95ec356d2fe57bc9c753d698b

~ruther/verilog-riscv-semestral-project

ref: 7ad5176683d16ac95ec356d2fe57bc9c753d698b verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 828 bytes

2929a779 — Rutherther 2 years ago

test: add basic testbenches