~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv 2929a779a9d6e451c15f91ac7124f4081e2a04b4

~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 828 bytes

2929a779 — Rutherther 2 years ago

test: add basic testbenches