~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/tests/custom/custom_tests.py -rw-r--r-- 1.9 KiB 
chore: remove unnecessary executable flags

Closes #4.

tests: add more custom tests

tests: add register dump, printing

feat: add support for official tests
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