~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/tests/comp_list.lst -rw-r--r-- 332 bytes
chore: remove unnecessary executable flags

Closes #4.
feat: move jumping to execute stage
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
chore: add new files to compilation list
tests: add python test environment for custom tests
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