~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.0 KiB
7ad51766 — Rutherther 2 years ago 
fix: remove duplicit instruction and pc in cpu
8f631f51 — Rutherther 2 years ago 
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
82d9e44f — Rutherther 2 years ago 
feat: add cpu top level entity