~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
feat: store c results in memory addr 0
feat: add basic testing programs
Do not follow this link