~ruther/verilog-riscv-semestral-project: tests/official/env 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f

~ruther/verilog-riscv-semestral-project

ref: 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f verilog-riscv-semestral-project/tests/official/env d---------

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests