~ruther/verilog-riscv-semestral-project: src/ram.sv 69ced879bbbaf6d106ac95a8ee8e6a6872177c83

~ruther/verilog-riscv-semestral-project

ref: 69ced879bbbaf6d106ac95a8ee8e6a6872177c83 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 1 year, 8 months ago

feat: add basic ram, alu, and register file