~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 345 bytes
a6f4c7fc — Rutherther 2 years ago 
chore: add new files to compilation list
34b74f06 — Rutherther 2 years ago 
tests: add python test environment for custom tests