~ruther/verilog-riscv-semestral-project: src 681756b70c4accd8c4caec6e97d8275a6359e5f9

~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/src d---------

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file