~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
feat: store c results in memory addr 0
feat: add basic testing programs
Do not follow this link