~ruther/verilog-riscv-semestral-project: testbench/tb_cpu_simple.sv 66fd5da9a15539865c07f3516a5e396674a2bf16

~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.3 KiB

773f4b99 — Rutherther 1 year, 7 months ago

test: add simple cpu test