~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv 66fd5da9a15539865c07f3516a5e396674a2bf16

~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.0 KiB

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches