~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv 66d141635b81de276634d3d9f97fe46c0ffb2f32

~ruther/verilog-riscv-semestral-project

ref: 66d141635b81de276634d3d9f97fe46c0ffb2f32 verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 837 bytes

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 2 years ago

test: add basic testbenches