~ruther/verilog-riscv-semestral-project: src/ram.sv 64d33d2582c219e00b6c1f7573501ee713da0967

~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file