~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 64d33d2582c219e00b6c1f7573501ee713da0967

~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB

32ebeea6 — Rutherther 2 years ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder