~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/programs/ma.c -rw-r--r-- 282 bytes
fb02ebb2 — Rutherther 2 years ago
Merge pull request #2 from Rutherther/feat/misaligned-reads

Support misaligned read
e5d2c0c5 — Rutherther 2 years ago
tests: add simple ma.c program for testing misaligned access