~ruther/verilog-riscv-semestral-project: src/ram.sv 52b05e5db08bd4360a157609d8529e01ad35cfd9

~ruther/verilog-riscv-semestral-project

ref: 52b05e5db08bd4360a157609d8529e01ad35cfd9 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 1 year, 8 months ago

feat: add basic ram, alu, and register file