~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 52b05e5db08bd4360a157609d8529e01ad35cfd9

~ruther/verilog-riscv-semestral-project

ref: 52b05e5db08bd4360a157609d8529e01ad35cfd9 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB

32ebeea6 — Rutherther 2 years ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder