~ruther/verilog-riscv-semestral-project: src/ram.sv 51a684d98d8d4e7e256565e1ad0ec13a72116fd8

~ruther/verilog-riscv-semestral-project

ref: 51a684d98d8d4e7e256565e1ad0ec13a72116fd8 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 1 year, 7 months ago

feat: add basic ram, alu, and register file