~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 345 bytes
a6f4c7fc — Rutherther 2 years ago 
chore: add new files to compilation list
34b74f06 — Rutherther 2 years ago 
tests: add python test environment for custom tests