~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/README.md -rwxr-xr-x 4.9 KiB 
docs: document pipeline a bit

docs: add basic documentation
Do not follow this link