~ruther/verilog-riscv-semestral-project

ref: 37437a002b69c937712b58ce3782f510248fcdcc verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB 
chore: add makefile for both verilog and c

test: add basic testbenches