~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv 34b74f067674498d19ea3797dfaa3330ce1514f0

~ruther/verilog-riscv-semestral-project

ref: 34b74f067674498d19ea3797dfaa3330ce1514f0 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches