~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 34b74f067674498d19ea3797dfaa3330ce1514f0

~ruther/verilog-riscv-semestral-project

ref: 34b74f067674498d19ea3797dfaa3330ce1514f0 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 1 year, 5 months ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 1 year, 5 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number