~ruther/verilog-riscv-semestral-project: .gitignore 32ebeea65b555fea871d5d5f91c13b27efcc6e57

~ruther/verilog-riscv-semestral-project

ref: 32ebeea65b555fea871d5d5f91c13b27efcc6e57 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes

9c81ece2 — Rutherther 2 years ago

chore: add gitignore