~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
65ab00a4 — Rutherther 2 years ago
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago
chore: add gitignore