~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 300c2dd744c0a39f8ca60ce97c3015c7af4c27cf

~ruther/verilog-riscv-semestral-project

ref: 300c2dd744c0a39f8ca60ce97c3015c7af4c27cf verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.8 KiB

32ebeea6 — Rutherther 2 years ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder