~ruther/verilog-riscv-semestral-project: testbench 2f09f768fe5d2888738e473802f708ad6fa8f794

~ruther/verilog-riscv-semestral-project

ref: 2f09f768fe5d2888738e473802f708ad6fa8f794 verilog-riscv-semestral-project/testbench d---------

773f4b99 — Rutherther 2 years ago

test: add simple cpu test

2929a779 — Rutherther 2 years ago

test: add basic testbenches