~ruther/verilog-riscv-semestral-project: src/ram.sv 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8

~ruther/verilog-riscv-semestral-project

ref: 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file